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1/20 ? semiconductor msm5416125a description the oki msm5416125a is a 128k-word 16-bit dynamic ram fabricated in oki's cmos silicon gate technology. the msm5416125a achieves high integration, high-speed operation, and low- power consumption due to quadruple polysilicon double metal cmos. the msm5416125a has conventional two cas type 256 k 16 dram compatible pinout. the msm5416125a is available in a 40-pin plastic soj or 44/40-pin plastic tsop. features ? fast page mode operation ? byte wide control: 2 cas control ? 131,072-word 16-bit organization ? pin compatible with 2 cas type 256 k 16 dram ? single 5 v power supply, 10% tolerance ? cas before ras refresh, hidden refresh, ras only refresh capability ? refresh: 512 cycles/8 ms ? package options: 40-pin 400 mil plastic soj (soj40-p-400-1.27) (product : msm5416125a-xxjs) 44/40-pin 400 mil plastic tsop (type ii) (tsopii44/40-p-400-0.80-k) (product : MSM5416125A-XXTS-K) xx indicates speed rank. product family ? semiconductor msm5416125a 131,072-word 16-bit dynamic ram : fast page mode type family msm5416125a-45 msm5416125a-50 t rac 45 ns 50 ns 60 ns msm5416125a-60 t aa 24 ns 26 ns 30 ns t rc 90 ns 100 ns 120 ns operating (max.) standby (max.) 715 mw 660 mw 605mw access time (max.) cycle time (min.) power dissipation t cac 14 ns 14 ns 15 ns t oea 14 ns 14 ns 15 ns 11 mw msm5416125a-40 40 ns 22 ns 80 ns 770 mw 14 ns 14 ns this version: jan. 1998 previous version: dec. 1996 e2l0049-17-y1
2/20 ? semiconductor msm5416125a pin configuration (top view) note: the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc we ras nc a0 a1 a2 a3 v cc v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc lcas ucas oe a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 21 22 40-pin plastic soj 44/40-pin plastic tsop ( ii ) (k type) 20 v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 nc nc we ras nc a0 a1 a3 v cc a2 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 24 23 25 v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 nc lcas ucas oe a8 a7 a6 a4 v ss a5 pin name function a0 - a8 address input ras row address strobe lcas lower byte column address strobe dq0 - dq15 data - input / data - output we write enable output enable power supply (5 v) ground (0 v) nc no connection v cc v ss oe ucas upper byte column address strobe row address column address : a0 - a8 : a0 - a7
3/20 ? semiconductor msm5416125a block diagram function mode ras h l input pin lcas * h l ucas h we h h h l l oe l l l h l l l l l h l l h l l h l * * * * * h lower byte read upper byte read word read refresh standby lower byte write dq pin dq0 - dq7 high-z high-z dq8 - dq15 high-z high-z d out d in high-z d out don't care high-z d out d out don't care d in upper byte write l lll h d in d in word write h lll h high-z high-z h timing generator ras ucas lcas refresh control clock column address buffers internal address counter row address buffers row deco- ders word drivers memory cells sense amplifiers column decoders 8 9 a0 - a8 i/o controller i/o controller we 16 i/o selector input buffers output buffers output buffers input buffers 16 8 8 8 8 8 8 8 8 dq0 - dq7 dq8 - dq15 on-chip v bb generator v cc v ss oe burst address counter 9 8 function table * : "h" or "l"
4/20 ? semiconductor msm5416125a electrical characteristics absolute maximum ratings rating C1.0 to 7.0 50 1 0 to 70 C55 to 150 v ma w c c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t i os p d t opr t stg parameter unit symbol condition ta = 25c ta = 25c ta = 25c recommended operating conditions input high voltage power supply voltage input low voltage v cc v ss v ih v il max. 5.5 0 6.5 0.8 v v v v typ. 5.0 0 min. 4.5 0 2.4 C1.0 (ta = 0c to 70c) parameter unit symbol capacitance input capacitance (a0 - a8) c in1 c in2 c i/o pf pf pf input capacitance ( ras , lcas , ucas , we , oe ) output capacitance (dq0 - dq15) max. 7 7 10 typ. (v cc = 5 v 10%, ta = 25c, f = 1 mhz) parameter unit symbol
5/20 ? semiconductor msm5416125a dc characteristics notes : 1. specified values are obtained with output open. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih . input leakage current output high voltage condition average power supply current (operating) power supply current (standby) output low voltage output leakage current average power supply current ( ras only refresh) parameter i oh = C1.0 ma i ol = 1.0 ma 0 v v i 6.5 v ; all other pins not under test = 0 v dqi disable 0 v v o 5.5 v ras , cas cycling, t rc = min. ras , cas = v ih ras = cycling, cas = v ih , t rc = min. max. v cc 0.4 10 10 130 2 130 min. 2.4 0 C10 C10 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2 1 1, 2 max. v cc 0.4 10 10 120 2 120 min. 2.4 0 C10 C10 symbol v oh v ol i li i lo i cc1 i cc2 i cc3 unit v v m a m a ma ma ma msm5416125a -45 msm5416125a -50 msm5416125a -60 max. v cc 0.4 10 10 110 2 110 min. 2.4 0 C10 C10 average power supply current (fast page mode) ras = v il , cas cycling, t pc = min. 130 1, 3 120 i cc7 ma 110 average power supply current ( cas before ras refresh) ras = cycling, cas before ras 130 1, 2 120 i cc6 ma 110 power supply current (standby) ras = v ih , cas = v il , d out = enable 5 1 5 i cc5 ma 5 max. v cc 0.4 10 10 140 2 140 min. 2.4 0 C10 C10 msm5416125a -40 130 140 5
6/20 ? semiconductor msm5416125a ac characteristics (1/2) random read or write cycle time read modify write cycle time parameter 100 145 90 130 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 fast page mode cycle time 31 30 fast page mode read modify write cycle time 65 60 access time from ras 50 45 access time from cas 14 14 access time from column address 26 24 access time from oe 14 14 access time from cas precharge 29 27 output buffer turn-off delay time 8 3 8 3 oe to data output buffer turn-off delay time 8 3 8 3 transition time 35 2 35 2 ras precharge time 40 35 10,000 50 10,000 45 100,000 50 100,000 45 14 14 10 8 7 6 10,000 14 10,000 14 50 45 5 5 36 20 31 18 24 15 21 13 row address set-up time 0 0 row address hold time 10 8 column address set-up time 0 0 column address hold time 8 6 column address hold time from ras 35 30 column address to ras lead time 26 24 ras pulse width ras pulse width (fast page mode) ras hold time ras hold time referenced to oe cas precharge time (fast page mode) cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time refresh period 8 8 note 4, 9, 10 4, 9 4, 10 4, 9, 10 5 5 14 12 9 10 11 11 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms symbol t rc t rwc t pc t prwc t rac t cac t aa t oea t cpa t off t oez t t t rp t ras t rasp t rsh t roh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t ref max. min. max. min. msm5416125a -45 msm5416125a -50 msm5416125a -60 max. 60 15 30 15 34 10 10 35 10,000 100,000 10,000 45 30 8 min. 120 165 33 80 3 3 2 50 60 60 15 10 8 15 60 5 20 15 0 10 0 10 45 30 cas pulse width output low impedance time from cas 0 0ns t clz 0 80 115 28 60 40 14 22 14 27 8 3 8 3 35 2 30 10,000 40 100,000 40 14 8 6 10,000 14 40 5 26 18 18 13 0 8 0 6 30 22 8 max. min. msm5416125a -40 0
7/20 ? semiconductor msm5416125a ac characteristics (2/2) parameter 0 9 0 8 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3 9 8 35 30 9 8 9 8 14 14 0 0 35 30 32 30 44 40 70 65 0 0 10 10 10 10 note 8, 11 11 13 7, 11 8 8 8 11 12 7, 11 11 9 8 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns symbol min. min. msm5416125a -45 msm5416125a -50 msm5416125a -60 min. 0 10 10 45 10 12 15 0 45 35 50 80 0 10 10 10 8 8ns 10 write command set-up time write command hold time write command pulse width write command hold time from ras oe command hold time write command to cas lead time write command to ras lead time data-in set-up time data-in hold time data-in hold time referenced to ras oe to data-in delay time ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) cas to we delay time column address to we delay time t wcs t wch t wp t wcr t oeh t cwl t rwl t ds t dh t dhr t oed t rwd t rpc t csr t chr t cwd t awd max. max. max. read command set-up time 0 0 read command hold time 0 0 read command hold time referenced to ras 0 0 11 6, 11 6 ns ns ns t rcs t rch t rrh 0 0 0 0 8 7 30 8 7 14 0 30 28 38 60 0 10 10 7 min. msm5416125a -40 8 max. 0 0 0
8/20 ? semiconductor msm5416125a notes: 1. an initial pause of 200 m s is required after power-up, followed by any 8 ras cycles. (example : ras -only-refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 1 ttl load and 50 pf. output timing reference levels are v oh = 2.0 v and v ol = 0.8 v. 5. t off (max.) and t oez (max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 6. t rch or t rrh must be satisfied for a read cycle. 7. these parameters are referenced to ucas , lcas , leading edge in an early write cycle, and to we leading edge in an oe control write cycle or a read modify write cycle. 8. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.) and t awd 3 t awd (min.) , the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. operation within the t rcd (max.) limit insures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11. these parameters are determined by the falling edge of ucas or lcas , whichever is earlier. 12. these parameters are determined by the rising edge of ucas or lcas , whichever is later. 13. t cwl should be satisfied by both ucas and lcas . 14. t cp is determined by the time both ucas and lcas are high. 15. input levels at the ac testing are 3.0 v/0.5 v.
9/20 ? semiconductor msm5416125a timing waveform read cycle valid data valid data ras a0 - a8 we dq8 - 15 ucas lcas "h" or "l" t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rac open dq0 - 7 open t aa t cac t oez t oea t roh t off oe t crp t rch t clz
10/20 ? semiconductor msm5416125a early write cycle ( lcas and ucas active) ras a0 - a8 ucas lcas "h" or "l" t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column we dq0 - 7 valid data dq8 - 15 valid data t ds t dh t ds t dh oe t rwl t cwl t wp t wcs t wch t wcr t dhr t crp open open
11/20 ? semiconductor msm5416125a late write cycle ( lcas and ucas active) ras a0 - a8 ucas lcas "h" or "l" t rc t ras t rp t ar t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column we dq0 - 7 valid data dq8 - 15 valid data t ds t dh t ds t dh oe t rwl t cwl t wp t oeh t wcr t rcs t oed t oed t crp
12/20 ? semiconductor msm5416125a read modify write cycle ( lcas and ucas active) ras a0 - a8 ucas lcas "h" or "l" t rwc t ras t rp t ar t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column we dq0 - 7 dq8 - 15 oe t rwl t cwl t wp t oeh t rwd t rcs t cwd t oea in in t ds t dh t ds t dh out out t oez t cac t rac t awd t oed t clz t clz t crp
13/20 ? semiconductor msm5416125a fast page mode read cycle ras a0 - a8 we dq0 - 7 ucas lcas oe row column t crp t crp t rp t rasp t cas column column t rcd t cp t cas t cas t pc t cp t rsh t ral t cah t asc t rad t rcs t rcs t rch t rrh t rcs t rac t aa t cpa t rch t ar t cac t clz t oea valid data t rch t rah t asr t cah t asc t cah t asc t aa t aa t cpa t cac t cac t off dq8 - 15 "h" or "l" valid data t clz t csh open open valid data valid data valid data valid data t off t oez t oea t oea t off t oez t oez t clz
14/20 ? semiconductor msm5416125a fast page mode early write cycle ras a0 - a8 we dq0 - 7 ucas lcas oe row column t crp t rp t rasp t cas column column t rcd t cp t cas t cas t pc t cp t rsh t ral t cah t asc t rad t ar t rah t asr t cah t asc t cah t asc t cwl dq8 - 15 "h" or "l" t csh t cwl t cwl t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp input data t ds t dh input data t ds t dh input data t ds t dh input data t ds t dh input data t ds t dh input data t ds t dh t crp
15/20 ? semiconductor msm5416125a fast page mode read modify write cycle ras a0 - a8 we dq0 - 7 ucas lcas oe t rasp dq8 - 15 "h" or "l" t rp t crp t rcd t cas t cp t cas t cp t cas t rsh t prwc t csh t asr t rah t asc t rad row column column t ar t cah t asc t cah column t asc t cah t ral t awd t cwl t awd t cwl t awd t rcs t cwd t wp t cwd t wp t cwd t wp t oea out in out in out in out in out in out in t oez t oea t oez t oea t cac t cac t cac t rac t dh t aa t dh t aa t clz t ds t clz t ds t clz t ds t cac t cac t cac t aa t aa t aa t ds t dh t ds t aa t ds t dh t dh t rac t clz t clz t clz t cwl t oez t dh t crp
16/20 ? semiconductor msm5416125a cas before ras refresh cycle ras a0 - a8 we dq0 - 7 ucas lcas oe t rpc t rp dq8 - 15 "h" or "l" open open t rc t ras t rp t rpc t csr t chr inhibit falling transition t off t off
17/20 ? semiconductor msm5416125a hidden refresh cycle ras a0 - a8 we dq8 - 15 ucas lcas "h" or "l" t rc t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t rah t asc t cah t ral row column t rcs t rrh open valid data dq0 - 7 open valid data t aa t cac t oez t oea t off oe t ras t off t rac t aa t cac t rac t roh t clz
18/20 ? semiconductor msm5416125a ras only refresh cycle ras a0 - a8 we dq0 - 7 ucas lcas oe row t crp t rpc t rp t ras t asr dq8 - 15 "h" or "l" open open t rc t rah
19/20 ? semiconductor msm5416125a (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj40-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.70 typ. mirror finish
20/20 ? semiconductor msm5416125a (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.49 typ. tsop ii 44/40-p-400-0.80-k mirror finish

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